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Error Correction without Use of Error Correction Code

IP.com Disclosure Number: IPCOM000077331D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Helwig, K: AUTHOR [+4]

Abstract

Error correction without using an error-correction code is achieved in the following manner?

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Error Correction without Use of Error Correction Code

Error correction without using an error-correction code is achieved in the following manner?

When upon the reading-out of a storage location of the main memory a parity error is detected by the parity check circuit PCC, this signal activates an automated error correction logic AEL. It causes the inversion of the word read out into the data register DR by an exclusive OR (XOR) circuit, the storing of the inverted word in the previously reading storage location, and its being read out again. Then, in case of a permanent error, i.e. an error caused by a permanently defective storage element capable of storing one of the two binary values only, the corrected word is now in data register DR in an inverted form. Therefore, no parity error is now indicated. Then the AEL initiates the renewed inversion of the data word by the XOR circuit. By this means, the corrected data word is available and delivered to its destination and also written again into the addressed storage location in order to enter the corrected information, thus regenerating the original storage conditions.

An intermittent error detector (IED) circuit has been provided to trace intermittent failures occurring during correction cycles.

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