Browse Prior Art Database

Error Avoidance Scheme

IP.com Disclosure Number: IPCOM000077344D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bowers, GH: AUTHOR [+2]

Abstract

Multiple storage bits may be used in place of a parity bit to check on stored data.

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This is the abbreviated version, containing approximately 100% of the total text.

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Error Avoidance Scheme

Multiple storage bits may be used in place of a parity bit to check on stored data.

Before a parity bit can be set the bits of data to be checked by the parity bit have to be known. Therefore, setting of the parity bit requires two cycles; one cycle to determine the data bits and then another cycle to set the parity bit. Where there is a time limitation, one of the cycles can be avoided while obtaining the checking characteristics of the parity bit, by using three storage bits to store each data bit. To store a binary "1" each of these three storage bits is made a 1, while to store a binary "0" each of the three storage bits is made a 0. To read the data out all three storage bits are read out in parallel into a voting circuit, which determines what is stored by a two out of three selection scheme.

This scheme can be used in storage protect for a storage system. One function of storage protect is to record all references and changes to protected areas of storage. This is accomplished by maintaining a reference bit and a change bit (R and C bits) for each protected block. Fetches to the storage system set the R bit, while stores set both. Traditionally, the R and C bits have been stored together with an associated parity bit. This would require two machine cycles to perform updating for the system specified. By separating the R and C bits and storing multiple copies as described above, the old two-cycle procedure is reduced to one cycle.

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