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IP.com Disclosure Number: IPCOM000077359D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Dumstorff, EF: AUTHOR [+2]

Abstract

A latch 4 is driven off module 1 to module 2 and on module 1 is used to gate logical functions on module 1, which affect other lines between module 1 and module 2. Normally latch 4 is set from logical conditions internal to module 1, but on module 2 the logical condition gated by the setting of latch 4 is required in given circumstances.

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Technique to Save I/O Pins

A latch 4 is driven off module 1 to module 2 and on module 1 is used to gate logical functions on module 1, which affect other lines between module 1 and module 2. Normally latch 4 is set from logical conditions internal to module 1, but on module 2 the logical condition gated by the setting of latch 4 is required in given circumstances.

To satisfy the latter requirement, it is desirable to provide the ability to set latch 4 without adding another line between the two modules. To do so, an AND gate 6 is added to module 2 which decodes when it is required to have AND gate 8 conditioned. The output of AND 6 also is used to force the output line 9 of latch 4 to a conditioned state. On module 1, an inverter 10 is added to invert line 9 and set latch 4 when line 9 is conditioned. Thus, the output of the latch is used to effect setting of latch 4 from an another module, effectively utilizing the output line 9 as a bidirectional data line.

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