Browse Prior Art Database

Increased Utilization of Instruction Counter

IP.com Disclosure Number: IPCOM000077371D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Waldecker, DE: AUTHOR

Abstract

In small data-processing systems it is generally desirable to accomplish a maximum number of functions with a minimum of hardware, using a limited number of separate logic building block types.

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Increased Utilization of Instruction Counter

In small data-processing systems it is generally desirable to accomplish a maximum number of functions with a minimum of hardware, using a limited number of separate logic building block types.

The data flow shown is typical for small processing units. Three registers, Q register 18, A register 20 and instruction counter 22 are included in data flow for arithmetic operations and instruction sequencing. Q register 18 is connected for an internal shift right which is required for multiply. A register 20 is connected to shift left internally as required for left shift instructions and for division.

Instruction counter 22 is normally not required to shift, even though the same logic building block is used for the instruction counter as for A Register 20 and Q register 18 which has an internal shift capability.

The internal shift capability of the instruction counter 22 is used to perform left shift operations, so that a quotient is accumulated in the instruction counter 22 during division operations. Upon completion of the divide instruction, the quotient is removed from instruction counter 22 and the instruction counter is restored with its original instruction count information from storage. This is achieved by storing the contents of instruction counter 22 in storage prior to the execution of a divide instruction, executing the divide instruction, and generating a pseudointerrupt to store the divide answer in storage an...