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Bit Count Checking for Binary Data Transmission

IP.com Disclosure Number: IPCOM000077382D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Peck, CC: AUTHOR [+2]

Abstract

This is a digital data-transmission system using synchronization or framing characters separating variable-length messages. A method for increasing the probability of detection of synchronization error (the loss or gain of bits) utilizes the Modulo 2 addition of the message bit count to the remainder, formed by the division of the data by a cyclic redundancy checking code polynomial. Such data-transmission systems use one or more synchronization or framing bit characters to separate messages. Relatedly, each message format is organized into "fields" such as an address and control field, a variable-length data field, and a redundancy-check field. Ordinarily, at the receiver, the digital message sequence can be viewed as a high-order polynomial. Error detection is provided by adding to the message a series of remainder bits.

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Bit Count Checking for Binary Data Transmission

This is a digital data-transmission system using synchronization or framing characters separating variable-length messages. A method for increasing the probability of detection of synchronization error (the loss or gain of bits) utilizes the Modulo 2 addition of the message bit count to the remainder, formed by the division of the data by a cyclic redundancy checking code polynomial.

Such data-transmission systems use one or more synchronization or framing bit characters to separate messages. Relatedly, each message format is organized into "fields" such as an address and control field, a variable-length data field, and a redundancy-check field. Ordinarily, at the receiver, the digital message sequence can be viewed as a high-order polynomial. Error detection is provided by adding to the message a series of remainder bits. The remainder bits are calculated by the division of the message bits by a so-called "cyclic code checking" polynomial. An excellent basic description of this coding procedure appears in "Digital Design" by R. K.

Richards, published by John Wiley & Sons, New York, 1971, at pages 221-271.

When the message plus remainder is transmitted error-free to a receiver, the receiver can check for so-called Modulo 2 addition errors, that is, same ones changing to zeros and some zeros changing to ones with the number of bits in the message remaining the same. The receiver customarily duplicates the computation of the remainder by dividing the received message sequence by the checking polynomial. If no errors or an even number of errors have occurred during transmission, then the remainder calculated at the receiver will be "all zeros". One of the most probable undetected errors will be a beginning or an ending synchronization pattern, changing to an all zero pattern during transmission. In this instance, a Modulo 2 addition error on a framing character creates a synchronization error (gaining or losing bits for the message). This type of sync error will not change the zero remainder.

The method contemplates the steps of counting the number of bits in the message, exclusive of synchronization or framing characters and Modulo 2 adding the bit count to the remainder prior to transmission. At the receiver, a bit count is Fade of the received digit sequence as well as a remainder being calculated by dividing the received sequence by the checking polynomial. The bit count calculated at the receiver is Modulo 2 added to the calculated remainder. If this is the same as the combined bit count-remainder in the message, then a synchronization error has not occurred.

Advantageously, at the transmitter, bit count in inserted into the shift register used to generate the remainder bits but prior to the calculation of such remainder bits, then the Modulo 2 addition can be conveniently performed in such shift register without the need for additional logic.

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