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Shift Register Counter

IP.com Disclosure Number: IPCOM000077393D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Alcantar, JM: AUTHOR [+2]

Abstract

A continually running shift register counter is controlled for recording a count through selected feedback, external setting, and internal resetting without a reset line to each stage.

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Shift Register Counter

A continually running shift register counter is controlled for recording a count through selected feedback, external setting, and internal resetting without a reset line to each stage.

Each stage, S1 through S5, is a latch and has appropriate decoding, not shown. Recording of a particular count is to begin when each and every stage is set or contains a "one". Once a stage is set, on the next clock time the succeeding stage will be set. Depending on the input along external set lines 10 and 12, the output of NOR gates 1 and 2, respectively, will control the setting of latch L and the output of NOR gate 4. The output of NOR gate 2 is applied to both latch L and inverter 8.

When it is desired to begin recording a count, appropriate signals are applied to lines 10 and 12 for the output of NOR gate 4 to be a "one". "Ones" continue to be applied on succeeding clock times to stage S1 until each stage contains a "one". When each stage contains a "one" the inverted output thereof is applied along lines 11, through NOR gate 3 and inverter 9 for resetting latch L. At this time, the feedback along lines 13 and 16 to NOR gate 6 and along lines 14 and 15 to NOR gate 7 is applied to NOR gate 5. The output of NOR gate 4 will now be a zero. Lines 14 and 16 represent the inverted output of stages S2 and S5, respectively.

With the above arrangement a definite beginning point in a free running register is identified. "Ones" and "zeros" can be loaded into the r...