Browse Prior Art Database

FET Storage Address Extender

IP.com Disclosure Number: IPCOM000077397D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Swech, HP: AUTHOR

Abstract

With the increasing use of FET (Field-Effect Transistor) shift registers as multipurpose low-cost buffers, it may be occasionally desirable to extend the length of the shift register by several bits. However, because of the FET shift register unique timing requirements, simple series connection of triggers or master/slave flip-flops in the feedback loop can not be used. A shift register is extended for a single timing period by simulation of FET shift register operation, using the shift register timing control in the following manner.

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FET Storage Address Extender

With the increasing use of FET (Field-Effect Transistor) shift registers as multipurpose low-cost buffers, it may be occasionally desirable to extend the length of the shift register by several bits. However, because of the FET shift register unique timing requirements, simple series connection of triggers or master/slave flip-flops in the feedback loop can not be used. A shift register is extended for a single timing period by simulation of FET shift register operation, using the shift register timing control in the following manner.

Referring to Fig. 1, an FET shift register 1 having stages from 1 to N is driven by a two-phase clock driver 3, which, in turn, is controlled by timing pulses T0 and T4. Polarity hold logic circuits #1 and 32, shown as blocks 5 and 7, are connected in series in the feedback-loop of the FET shift register and function as storage media, which are sequentially driven by the T0 and T4 timing pulses used to control clock driver 3.

In the embodiment shown by way of example, the cycle timing as shown in Fig. 2 is 945 nanoseconds, divided into 9 timing periods (T0 through T8) of 105 nanoseconds each. At time T8, data is shifted from polarity hold circuit 7 into Address 1 of the FET shift register 1, and data from the N position is shifted into polarity hold circuit 5. At time T4, data is transferred from polarity hold circuit 5 into polarity hold circuit 7. The time between T5 and T8 allows data to be present at...