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Full Erasure of Interblock Gap between Records on Magnetic Tape

IP.com Disclosure Number: IPCOM000077408D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Martin, VC: AUTHOR

Abstract

Shown is a schematic block diagram of a circuit which may be used in a tape drive to ensure full erasure of interblock gaps. Full erasure is accomplished by monitoring the end of a write signal with time sensing circuits 10, and utilizing logic to immediately turn on a high-write current to all heads as soon as the writing of a record block has been terminated. The high constant-write current effectively erases any magnetization in the interblock gap.

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Full Erasure of Interblock Gap between Records on Magnetic Tape

Shown is a schematic block diagram of a circuit which may be used in a tape drive to ensure full erasure of interblock gaps. Full erasure is accomplished by monitoring the end of a write signal with time sensing circuits 10, and utilizing logic to immediately turn on a high-write current to all heads as soon as the writing of a record block has been terminated. The high constant-write current effectively erases any magnetization in the interblock gap.

The time sensors 10 used in detecting the end-of-write data are effectively energy sensors which time out and drop their signal output when a data signal is no longer present on their input. The response time or time-out period for the time sense circuits depends upon the choice of capacitors 12 and 14.

The logic blocks used are negative logic blocks. For example, the AND gates will have an output only if both inputs to each AND are down, rather than up.

In operation, OR gate 16 collects three write signals from three separate tracks. The write signals collected are chosen so that during a record block, there will always be one write signal present for any format of data being written. At the leading rising edge of first write signal, the output of OR 16 also rises. This rising signal degates AND 18 in latch 20. AND 18 is degated because it is a negative logic circuit. With AND 18 inhibited, the output from latch 20 drops, and there is no longer high-wr...