Browse Prior Art Database

Module Selection for Array Logic

IP.com Disclosure Number: IPCOM000077416D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Dorler, J: AUTHOR [+3]

Abstract

Wafer grading of read-only-memories (ROM's) at stock, necessitates the testing of the Product with only logical "1's" stored in the memory array. Minimal information can be gained by exercising the address circuits since the output remains a 1. Product defects such as those that would hold the output circuit at a 1 would go undetected.

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Module Selection for Array Logic

Wafer grading of read-only-memories (ROM's) at stock, necessitates the testing of the Product with only logical "1's" stored in the memory array. Minimal information can be gained by exercising the address circuits since the output remains a 1. Product defects such as those that would hold the output circuit at a 1 would go undetected.

In order to identify this latter type error in a conventional ROM arrangement comprising a plurality of address circuits 10...n, a word decoder 12, a plurality of array drivers 14, a memory array 16, and sense and output circuits 18 and 20, respectively, are provided. A module select circuit 22 is located at the decode level and connected to the word decoder via line 24.

In this manner, the module select circuit 22 can be exercised simultaneously with address energization. When the module select is activated, all array drives are forced to a "0" state causing the outputs to switch to the 0 state. This will assure that the majority of the circuitry for the array is operative. This configuration also allows the measurement of access delay for bit selection.

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