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Self Alignment Technique for Fabricating High Performance FET's

IP.com Disclosure Number: IPCOM000077432D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Johnson, WS: AUTHOR

Abstract

In this method a block of chemically vapor-deposited glass over the gate region is used to achieve self-alignment during an ion implantation step.

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Self Alignment Technique for Fabricating High Performance FET's

In this method a block of chemically vapor-deposited glass over the gate region is used to achieve self-alignment during an ion implantation step.

As indicated in Fig. 1, a thin layer 10 of thermal oxide is formed on semiconductor substrate 11. A Si(3)N(4) layer 12 is deposited on layer 10, and a relatively thick layer 14 of chemically vapor-deposited glass formed over layer 12. As indicated in Fig. 2, source and drain openings 16 and 18 are formed through layer 14 using conventional photolithographic techniques. Source 20 and drain region 22 are formed by ion implantation, through the thin nitride-oxide layers 12 and 10 in the openings. phosphorus or arsenic is preferably implanted using 150 Kev with an ion density of 101/16/ atoms/cm sq. A photoresist layer 23 is subsequently deposited over the surface of the device, exposed, and developed to cover the gate region 24, as shown in Fig. 3. The unprotected CVD glass layer 14 is etched, and the photoresist 23 subsequently removed. A suitable etchant removes the Si(3)N(4) layer 12 in all areas, except the gate region 24 which is protected by the layer of glass.

An ion implant step, as shown in Fig. 4, is made with a P-type impurity, as for example, boron, such that the ions do not penetrate the gate region but do so in all other regions. In this way, the field regions are protected against possible inversion with subsequent parasitic leakage. After remo...