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Metal Insulator Semiconductor FET Fabrication Process

IP.com Disclosure Number: IPCOM000077437D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Chiu, TL: AUTHOR [+3]

Abstract

In this process a P-type doped SiO(2) layer 10 is deposited on the surface of an N-type semiconductor substrate 12. Using photolithographic and etching techniques all of layer 10 is removed, except over the intended source and drain regions. This leaves portions 14 and 16. As shown in Fig. 3, a thin film 18 of an insulator is deposited over the surface of the wafer, including layer portions 14 and 16. The thickness of layer 18 is such that it will prevent impurity penetration, but will allow a small amount of oxygen to penetrate and form a thermal oxide beneath the insulator.

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Metal Insulator Semiconductor FET Fabrication Process

In this process a P-type doped SiO(2) layer 10 is deposited on the surface of an N-type semiconductor substrate 12. Using photolithographic and etching techniques all of layer 10 is removed, except over the intended source and drain regions. This leaves portions 14 and 16. As shown in Fig. 3, a thin film 18 of an insulator is deposited over the surface of the wafer, including layer portions 14 and 16. The thickness of layer 18 is such that it will prevent impurity penetration, but will allow a small amount of oxygen to penetrate and form a thermal oxide beneath the insulator.

As indicated in Fig. 4, the wafer is exposed to a relatively high temperature sufficient to cause the impurity in regions 14 and 16 to diffuse into body 12, to form source and drain regions 20 and 22. Simultaneously, a thin thermal oxide layer 24 is formed beneath layer 18 at the surface of body 12. The contact openings are subsequently made for the source and drain regions and a layer metal evaporated on the top surface. Using the conventional photolithographic and etching techniques, source terminal 26, drain terminal 28 and gate terminal 30 are fabricated. In forming an N channel field-effect transistor (FET) the dopants are reversed, that is a P-type P-doped substrate 12 and an N-doped layer 10 is utilized.

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