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Simultaneous Fabrication of P Channel Enhancement and Depletion Mode IGFETs

IP.com Disclosure Number: IPCOM000077451D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Barile, CA: AUTHOR [+3]

Abstract

This process permits the fabrication of enhancement mode and depletion mode P-channel insulated gate field-effect transistors (IGFETs) on the same wafer. The process is similar to a standard P-channel self-aligned gate process for producing enhancement mode devices. Depletion mode devices are selectively produced on the same chip, by removing silicon nitride from the depletion mode gate insulator regions before depositing the polysilicon gates and making boron source and drain diffusions. The process steps are as follows: 1) Provide Si substrate 2) Initial oxide 3) Open areas for source, drain and channel 4) Grow gate oxide 5) Deposit Si(3)N(4) 6) Remove Si(3)N(4) over depletion mode devices. Leave Si(3)N(4) over enhancement mode devices.

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Simultaneous Fabrication of P Channel Enhancement and Depletion Mode IGFETs

This process permits the fabrication of enhancement mode and depletion mode P-channel insulated gate field-effect transistors (IGFETs) on the same wafer. The process is similar to a standard P-channel self-aligned gate process for producing enhancement mode devices. Depletion mode devices are selectively produced on the same chip, by removing silicon nitride from the depletion mode gate insulator regions before depositing the polysilicon gates and making boron source and drain diffusions.

The process steps are as follows: 1) Provide Si substrate 2) Initial oxide 3) Open areas for source, drain and channel 4) Grow gate oxide 5) Deposit Si(3)N(4) 6) Remove Si(3)N(4) over depletion mode devices. Leave Si(3)N(4) over enhancement mode devices. 7) Deposit polysilicon and etch gate pattern 8) Open source and drain diffusion windows 9) Source and drain BBr(3) diffusion
10) Deposit pyro SiO(2)
11) Open contact holes
12) Deposit Al, subetch and sinter.

This process produces enhancement mode devices (polysilicon gate- Si(3)N(4)-SiO(2)-Si) with a negative threshold voltage and depletion mode devices (polysilicon gate-SiO(2)-Si) with a positive threshold voltage. The difference in threshold voltages is due to a difference in the charge levels in the two gate structures. This process produces a net negative charge in the polysilicon-SiO(2) structure and a net positive charge in the polysilicon-Si(3)N(4...