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Message Signal Detector Circuit

IP.com Disclosure Number: IPCOM000077477D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Austruy, P: AUTHOR [+2]

Abstract

This circuit determines whether the signal received by a receiver is due to noise or is a message signal, and it determines the beginning and the end of a message.

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Message Signal Detector Circuit

This circuit determines whether the signal received by a receiver is due to noise or is a message signal, and it determines the beginning and the end of a message.

To avoid use of wide dynamic circuits, the various signal processing operations including message detection are performed on the received signal after regulation by AGC circuits. But regulation tends to maintain constant the average amplitude of the regulated signal; this action impedes a message detection operation based on level and level variation of the signal.

The present circuit uses two properties of the received signal: in a message, the received signal shows a frequency component at the frequency FCL of the data clock; even after regulation, the average amplitude of the component remains superior to the average amplitude of a component at the frequency FCL, which may occur randomly in a noise signal;

- at the end of a message, the received signal amplitude decreases and the regulated signal follows this variation before being readjusted by AGC circuits.

As shown on the figure, a signal received at the input IN enters AGC 8, output 9 of which delivers the regulated signal to reception circuits, not shown, and to the detector device described here. Signal at 9 is full-wave rectified in rectifier 10, then provided to peak detector 4 and to circuits 12. Filter 12 selects frequency FCL and squarer 15 delivers clock pulses. Full-wave rectifier 13 followed by low-pass filter 14 delivers on line 1, a DC level corresponding to the average amplitude of the component selected by filter 12.

During message reception, component FCL is continuously present at 12', this resulting in a high level on line 1. In comparator 2, this level is found higher than reference level CLRL and a low level on output line 3 is generated. Simultaneously, at each data time referenced by the clock...