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Time Shared Shift Accumulator

IP.com Disclosure Number: IPCOM000077478D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Esteban, DJ: AUTHOR

Abstract

A circuit reduction of a shift accumulator is achieved by time sharing its full adders and using a dump circuit. This accumulator performs parallel accumulation and right shift of word of 16-bit length.

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Time Shared Shift Accumulator

A circuit reduction of a shift accumulator is achieved by time sharing its full adders and using a dump circuit. This accumulator performs parallel accumulation and right shift of word of 16-bit length.

The partial products of a multiplication are applied from a multiplier to full adders A1, A2, A3 and A4 through lines L1 up to L4. Each word includes 15 bits "Bi" plus one sign bit "S" and is loaded in the full adders in four bit groups such as: B0 B1 B2 B3

B4 B5 B6 B7

B8 B9 B10 B11

B12 B13 B14 S.

Consequently bits, B0 B4 B8 B12 are loaded in the four stages of shift register SR1 through full adder A1. The other vertical groups of the above matrix are loaded, respectively, in the four stages of shift register SR2, SR3 and SR4 through full adders A2, A3 and A4.

The right shift of the successive groups is achieved by picking out the contents of shift register SR1 on its third stage by line L5.

The sequence of bits, so picked out, is introduced in A4 through an OR gate and an AND gate under control of control signal C1. By making the bits circulating through the full address and the shift registers by line L5, adding of the right shifted bits of a first group with the bits of the next one is made possible.

The carry out (Co) of the leftmost stage (A4) is applied to the carry in (Ci) of the rightmost stage (A1); and each carry out of an intermediate stage (Ai) is tied to the carry in of the preceding stage (A+1). This involves the propaga...