Browse Prior Art Database

Sample and Hold/Integrate and Hold Circuit

IP.com Disclosure Number: IPCOM000077479D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Schulz, RA: AUTHOR

Abstract

A circuit is shown which combines the functions of integrate and hold, sample and hold, and reset to zero in a single circuit.

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Sample and Hold/Integrate and Hold Circuit

A circuit is shown which combines the functions of integrate and hold, sample and hold, and reset to zero in a single circuit.

Operational amplifiers A1, A2, A3, A4 and A5 may be combined in a single circuit element. Operational amplifier Aout operates as a buffer to prevent output loads from discharging capacitor C. Each of the gated operational amplifiers A1, A2, A3 and A4 are enabled by the application of an appropriate voltage to the gate input such as INTEGRATE for A1, SAMPLE for A2, HOLD for A3 and RESET for A4.

To execute a sample and hold operation for example, the sample gate is activated allowing operational amplifier A2 in conjunction with amplifiers A5 and Aout to sample the input voltage Ein. After the sample has been taken, the sample gate is deactivated and the hold gate is activated allowing A3 in conjunction with A5 and Aout to maintain Eout at a constant level.

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