Browse Prior Art Database

Clocked Signal Assurance Circuit

IP.com Disclosure Number: IPCOM000077506D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kosieniak, AL: AUTHOR [+2]

Abstract

The clocked signal assurance circuit (CSAC) insures that a signal has maintained a stable input level before switching the output, thereby avoiding adverse effects of extraneous pulses or drop-outs that might otherwise cause false starts and disruptions in binary synchronous communication adapter (BSCA) operation.

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Clocked Signal Assurance Circuit

The clocked signal assurance circuit (CSAC) insures that a signal has maintained a stable input level before switching the output, thereby avoiding adverse effects of extraneous pulses or drop-outs that might otherwise cause false starts and disruptions in binary synchronous communication adapter (BSCA) operation.

When -IN and -OUT are at the same level, +RESET is on and the ring counter is held reset at count 0. If -IN changes, +RESET turns off and the ring counter is incremented by +CLOCK. If -IN maintains its changed level until the ring counter increments to count 3, the flip latch 5 is changed and -OUT is switched to the same level as -IN. If -IN does not maintain its changed level (as in the case of extraneous pulses or line drop-outs) +RESET will again come on and return the ring counter to count 0. In this case, -OUT will not change. The circuit operates in the same manner for both positive and negative input transitions. The length of time that the input must be maintained at a stable level before the output will be switched is determined by the period of +CLOCK.

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