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Microprogram Testing of Error Correction Logic

IP.com Disclosure Number: IPCOM000077524D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Kadner, K: AUTHOR [+2]

Abstract

Microprogram control means are provided within the central processor of a data-processing system for checking the accuracy of the ECC (error-correction code) logic provided therein, for single-error detection and correction of a monolithic main store. An example of the type of processor which can make advantageous use of the present means is shown in U. S. Patent 3,656,123 issued April 11, 1972, to R. J. Carnevale et al. The diagnostic checking means has been designed so that the check bits can be written into and read from the monolithic main store 10, with a minimum of additional circuitry. The diagnostics are executed primarily with circuitry existing in the processor.

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Microprogram Testing of Error Correction Logic

Microprogram control means are provided within the central processor of a data-processing system for checking the accuracy of the ECC (error-correction code) logic provided therein, for single-error detection and correction of a monolithic main store. An example of the type of processor which can make advantageous use of the present means is shown in U. S. Patent 3,656,123 issued April 11, 1972, to R. J. Carnevale et al. The diagnostic checking means has been designed so that the check bits can be written into and read from the monolithic main store 10, with a minimum of additional circuitry. The diagnostics are executed primarily with circuitry existing in the processor.

A normal write operation into store 10 involves a read operation to select a double word, one of which is to be replaced. During the write operation, thirty-two data bits (one word) are received from the processor register 11. The parity bits are stripped from the word. The data bits are combined with an additional thirty- two bits from the addressed double word received by way of an output register 12, an exclusive OR circuit 13, and a combining register 14. These sixty-four bits are sent to a write generator circuit 15 which stores the sixty-four data bits and generates eight ECC check bits. The data and check bits are transferred from 15 to the addressed double-word position in 10.

During a normal read operation, data (sixty-four bits plus the eight ECC bits) is read from 10. The data and check bits are stored in the resisters 12 and 18, respectively. A read generator 16 produces a set of ECC check bits in the same way as did the circuits 15. The check bits from 16 are compared in the detection circuits 17 with the check bits from 15 (which are now in 18). In the event of a mismatch between the check bits, circuits 17 produce a corrected output at 13, but only if a single-bit error exists. Circuits 17 also indicate the type of error.

In the diagnostic parity mode, the diagnostic parity line 19 is brought up causing the four data parity bits from 11 to bypass the ECC check bits of 15 so as to be written into the selected address of the s...