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Read And Test to Reduce Redundancy Requirements in Memories

IP.com Disclosure Number: IPCOM000077536D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Cocke, J: AUTHOR

Abstract

In the construction of large scale integrated (LSI) memories, it is not economically practical to produce completely failure-free modules. In the conventional use of error-correcting codes, the memory is generally considered a binary symmetric channel, i.e., each element thereof is assumed to be capable of erroneously changing a "0" to a "1" and a "1" to a "0".

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Read And Test to Reduce Redundancy Requirements in Memories

In the construction of large scale integrated (LSI) memories, it is not economically practical to produce completely failure-free modules. In the conventional use of error-correcting codes, the memory is generally considered a binary symmetric channel, i.e., each element thereof is assumed to be capable of erroneously changing a "0" to a "1" and a "1" to a "0".

In the technique described herein, the memory is treated essentially as a binary erasure channel. In case of a malfunction, the error signal results in a fixed logical value, either "0" or "1".

Thus an error occurs only when the data stored has the correct value opposite to the erroneous fixed value. To determine if such an error condition exists, after each READ operation, the data read has its bits complemented and the complemented data is written into the same address and READ. If any bits from the two READ's have the same value, the location read contains at least one malfunctioning circuit.

The LSI memories are initially tested to find out whether they will support error correction in this signal mode, i.e., the maximum number of failures in a given number is within the ability of the correction scheme which is selected. Then, during the usage of these LSI memories, WRITES would be performed normally. However, each READ would be accompanied by a testing phase. With this technique, therefore, the required redundancy is substantially less than that which would be required if standard correction techniques were to be employed.

An illustrative embodiment of the technique is the following:

Let it be assumed that a(1),..., a(j), represent data being stored in good memory cells; d(1),..., d(i), represent data being stored in failed cells which produce errors,...