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Browse Prior Art Database

Three Phase Five Device Dynamic Shift Register Cell

IP.com Disclosure Number: IPCOM000077540D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Pleshko, P: AUTHOR

Abstract

Five insulated gate field-effect transistors (IGFET's) are arranged to provide a three-phase shift register cell which has the advantage of requiring one less I/O pin, important in pin-limited applications.

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Three Phase Five Device Dynamic Shift Register Cell

Five insulated gate field-effect transistors (IGFET's) are arranged to provide a three-phase shift register cell which has the advantage of requiring one less I/O pin, important in pin-limited applications.

The five IGFET's, labelled Q1-Q5, are arranged as indicated in Fig. 1, with clock source phi 1 and/or phi 2 connected to source electrodes of Q1, Q2, Q3 and Q5, as indicated. Clock source phi 3 is connected to the control electrode of Q5, while device capacitances C1 and C2 are as indicated by the dotted lines to ground.

Referring to both Figs. 1 and 2, upon application of phi 1, capacitance C1 is charged. If an input is applied to the control electrode of Q2, then C1 is discharged. Upon application of phi 2, capacitance C2 is charged and upon application of phi 3 to the control electrode Q5, if no input was applied previously to Q2 allowing discharge of C1, then the control electrode of Q4 would be energized allowing discharge of C2 through Q4 and Q5. If an input were applied to Q2 allowing discharge of C1, then upon application of phi 3 there would be no path available for the discharge of C2.

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