Browse Prior Art Database

Instruction Translator

IP.com Disclosure Number: IPCOM000077561D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Kemp, JC: AUTHOR

Abstract

During an emulation operation, it is desirable to convert an instruction from the format of the emulated processor to a format that can be used by the host processor.

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Instruction Translator

During an emulation operation, it is desirable to convert an instruction from the format of the emulated processor to a format that can be used by the host processor.

The drawing shows a translator for converting a 17-bit instruction stored in operation buffer 10 to a 20-bit instruction stored in operation register 20, under the control of translation control 30 and gates 32, 34 and 36. A 5-bit op code is used to address translation control 30 to obtain control lines 21 through 27, in addition to an invalid tag and a privileged tag and 6 bits of operation code information. Lines 21 through 27 are used to control gates 32, 34 and 36 to fill operation register 20 from the appropriate fields of operation buffer 10, or from a data supplied by translation control 30.

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