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Digital Transversal Filter with Read Only Memory

IP.com Disclosure Number: IPCOM000077595D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR

Abstract

This is a digital transversal filter of the type where successive analog signal samples b(i) are digitally delta coded every T seconds, and where N successive delta coded values b(i) c(i) are summed to form analog signal samples (Image Omitted) C(i) being a weighting coefficient. The filter comprises a delta modulator 3 for converting an analog input 1 into a succession of digital delta modulation encoded signals b(i). The digital signals are serially applied every T seconds to an N-position shift register 23 through a two position logic gate 7. The logic gate couples a feedback path 25 from the shift register output to the register input, when the gate is in a first switching position (or first stable state).

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Digital Transversal Filter with Read Only Memory

This is a digital transversal filter of the type where successive analog signal samples b(i) are digitally delta coded every T seconds, and where N successive delta coded values b(i) c(i) are summed to form analog signal samples

(Image Omitted)

C(i) being a weighting coefficient. The filter comprises a delta modulator 3 for converting an analog input 1 into a succession of digital delta modulation encoded signals b(i). The digital signals are serially applied every T seconds to an N-position shift register 23 through a two position logic gate 7. The logic gate couples a feedback path 25 from the shift register output to the register input, when the gate is in a first switching position (or first stable state). The gate connects the digital signals over an input path 5 to the register when the gate is in a second switching position (or a second stable state). Clocking and counting means 9, 11, 13, 15, 17 operate to place the logic gate 7 into the first stable state for forming a reentrant register, and then for recirculating the entire register content within T/N seconds. Every T seconds the logic gate is put into the second stable state 19. At this time, another digital signal is transferred into the N-position shift register. The clocking means includes the log N-bit counter 9, which disables the logic gate into the second stable state every log(2) N intervals.

A read-only memory 27, 29, 31, 33 is addressed one bit at a time by the output of the shift register on connecting path 25, and the contents of the counter 9 over its connecting path 14. Thus, when the contents of the register are recirculating, there occurs N table look-ups of the read-only memory. The successive addresses consist of the successive bit contents of the regi...