Browse Prior Art Database

Stuck Bit Correction in Computer Memory

IP.com Disclosure Number: IPCOM000077615D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

This system is capable of detecting and correcting a "stuck bit" in a word read from storage without the need for an error-correcting code. Only the parity bit and one additional storage element are required. A "stuck bit" is defined as a storage location which, rather than being capable of storing both binary values "zero" or "one", can store only one of these values.

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Stuck Bit Correction in Computer Memory

This system is capable of detecting and correcting a "stuck bit" in a word read from storage without the need for an error-correcting code. Only the parity bit and one additional storage element are required. A "stuck bit" is defined as a storage location which, rather than being capable of storing both binary values "zero" or "one", can store only one of these values.

In operation, a data word to be checked is read from storage 2 by a conventional addressing means and is stored in data register 4. The true data on line 5 is transmitted through gate 9 and 12 to parity check block 14, which checks the parity of the word. If no error is found, the data is transmitted through OR block 15 for use in data processor 16.

If an error is detected due to incorrect parity, complement line 8 is strobed and the complement of the data is transmitted from data register 4 on line 6 through gates 10 and 12, back to the previously addressed storage location in storage 2. In this embodiment, the complemented data is transmitted through data processor 16, although a direct connection could also be made from OR gate 12 to storage 2.

During the read cycle, the complemented data in the addressed location is read out to data register 4. A marking bit associated with the complemented data indicates to the system that the data is in complemented form. The complemented data is again inverted by strobing line 6 through gates 10 and 12 to the system. T...