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Feedback System for Maintaining Constant Window Ratio in Binary Data Separation Apparatus

IP.com Disclosure Number: IPCOM000077617D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Kurzweil, F: AUTHOR [+3]

Abstract

In a binary data signal detection apparatus employing double frequency (2f) type code, a bit cell period is divided into data And clock window portions (Fig. 2g). A 1f ramp signal (Fig. 2b) developed by window generator 10 is used to generate separate windows for separating the data and clock, and for passing these signals through separate channels, which include diodes D1 and D2, respectively. The clock signal is delayed for 1/2 of a bit cell time, the bit cell time being equal to the period of the 1f ramp frequency signal. The separated data signals are combined with the delayed clock signals, and an average data-correction signal is generated as a function of the displacement of the data signal or the delayed clock from the center of the ramp.

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Feedback System for Maintaining Constant Window Ratio in Binary Data Separation Apparatus

In a binary data signal detection apparatus employing double frequency (2f) type code, a bit cell period is divided into data And clock window portions (Fig. 2g). A 1f ramp signal (Fig. 2b) developed by window generator 10 is used to generate separate windows for separating the data and clock, and for passing these signals through separate channels, which include diodes D1 and D2, respectively. The clock signal is delayed for 1/2 of a bit cell time, the bit cell time being equal to the period of the 1f ramp frequency signal. The separated data signals are combined with the delayed clock signals, and an average data- correction signal is generated as a function of the displacement of the data signal or the delayed clock from the center of the ramp. The frequency of the ramp generator is controlled by the average error-correction signal.

The ratio T(D): T(C) = proportional to:1 is maintained between the clock and data intervals by integrating in integrator 12 a constant voltage (weighted by 1 or proportional to ) over each interval, amplifying and inverting the signals in circuit 14, and then comparing the integrated signals in a comparator 16 having reference voltages V(A) and V(B), as illustrated in Fig. 2b. The error signal that is generated is reduced in the feedback loop to substantially zero for a steady state condition, by varying the reference voltages V(A) and V(B). B...