Browse Prior Art Database

Detection System

IP.com Disclosure Number: IPCOM000077620D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

McDonald, EG: AUTHOR

Abstract

Data detectors in magnetic recording systems employing variable-frequency bit period gate signals, exhibit performance degradation at low amplitude signal and minor defect area conditions. Such degradation during such conditions can be avoided by phase locking such detectors to a frequency-tracked reference signal.

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Detection System

Data detectors in magnetic recording systems employing variable-frequency bit period gate signals, exhibit performance degradation at low amplitude signal and minor defect area conditions. Such degradation during such conditions can be avoided by phase locking such detectors to a frequency-tracked reference signal.

Also described is a technique for generating clock and data signals useful for deskewing a phase-encoded signal, in which the data frequency varies as the result of tape velocity variations. Rather than depending on a pulse generator to generate data signals, a bit-synchronous detector demodulates data. Superior tracking capability is retained by using variable-frequency control gate concepts, while enhancing detection at low-signal levels. A squelch generator has a memory which allows a data clock to continue at its last velocity-determined, phase-locked condition so that bit-synchronous detection and clocking continues during periods of signal degradation.

Referring to Figs. 1 and 2, the timing relation of the circuit elements is described. Limited Data 1 and its complement are inputs to a pulse generator circuit which produces two sets of peak pulses. - Peak Pulses 2 correspond to negative transitions on Limited Data, and + Peak Pulses 3 correspond to positive transitions on Limited Data. Sensitivity of the pulse generator is such that peak pulses are generated only when the signal amplitude is sufficient to allow generation of a valid or high-quality peak pulse.

Two AND's and an OR follow the pulse generator and provide logic for controlling Squelch Pulse 5. At the beginning of the zeroes burst, Force Gate 4 is up (active) and allows only - Peak Pulses 2 to effect squelch. This action phase synchronizes Squelch Clock 6 with "data time". "Data time" is defined by the transition which is always present at the center of each phase-encoded bit cell. Having synchronized Squelch Clock w...