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Memory Addressing System

IP.com Disclosure Number: IPCOM000077629D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Koch, KF: AUTHOR

Abstract

In a memory bank system, the space of a memory unit MU is subdivided into a number of independently addressable memory blocks MB of possibly different capacities. For the proposed memory addressing system the capacity of the smallest MB must be a power of 2. The capacity of all other MBs must be a multiple of the size of the smallest MB. In order to avoid fragmentation of MB space in a paging system, the page size should be equal to the MB space or a multiple thereof. Associative addressing of the MBs is achieved by storing in each MB the lowest and highest byte address LMBA and HMBA of the segment block.

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Memory Addressing System

In a memory bank system, the space of a memory unit MU is subdivided into a number of independently addressable memory blocks MB of possibly different capacities. For the proposed memory addressing system the capacity of the smallest MB must be a power of 2. The capacity of all other MBs must be a multiple of the size of the smallest MB. In order to avoid fragmentation of MB space in a paging system, the page size should be equal to the MB space or a multiple thereof. Associative addressing of the MBs is achieved by storing in each MB the lowest and highest byte address LMBA and HMBA of the segment block.

The high-order bits of the byte address which are fed to all MBs of a MU via the byte address bus BAB, are compared in each MB with the stored values of LMBA and HMBA. If the integer represented by the MB bits comes within the range of the low order and the high order MB address, the corresponding MB is selected. The low-order bits of the byte address are then used as an offset to address the desired byte in the MB. The internal addressing logic IAL of each MB is shown in the figure.

The number of bits required for the MB offset depends on the size of the MB. It is equal to the number of bits required to specify the largest MB offset. The number of MB address bits depends on the largest address present in a computer system, and on the capacity of the smallest MB of the MU. It is equal to the number of bits on the B:AB minus the number of offset bits of the smallest MB. Therefore, in all MBs having a size larger than that of the smallest MB, several bits ("shared bits") a...