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Arithmetic Logical Unit A Register Addressability to Improve Microprocessor Compare Capability

IP.com Disclosure Number: IPCOM000077642D
Original Publication Date: 1972-Aug-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Dumstorff, EF: AUTHOR [+2]

Abstract

In a microprocessor having a limited number of local store registers (LSR), the number of instructions required to code the program and faster execution may be obtained by assigning the register in the A-side of the arithmetic and logic unit (ALU) an LSR address. Using the decode of a selective address assigned to such A-side register to inhibit the gating into and resetting of the A-Register, requires one additional input to each of the two affected AND gates 2 and 3.

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Arithmetic Logical Unit A Register Addressability to Improve Microprocessor Compare Capability

In a microprocessor having a limited number of local store registers (LSR), the number of instructions required to code the program and faster execution may be obtained by assigning the register in the A-side of the arithmetic and logic unit (ALU) an LSR address. Using the decode of a selective address assigned to such A-side register to inhibit the gating into and resetting of the A- Register, requires one additional input to each of the two affected AND gates 2 and 3.

The normal operation of the ALU is to first load the B-REGISTER from the data path (DP) during GATE-B-TIME, load the A-REGISTER from the data path (DP) (during GATE-A-TIME), execute the operation specified by ALU OPERATION, and then during GATE-R-TIME, gate the result to the condition code logic and data path out (DPOUT). At this time the result is latched in the same LSR that was used to load the A-REGISTER.

When the instruction addresses the A-REGISTER during GATE-A-TIME, the operation is as follows: Load the B-REGISTER from data path (DP) during GATE-B-TIME. Then as a result of addressing the A-REGISTER, the gate-in and reset of the A-REGISTER is inhibited during GATE-A-TIME to preserve the original contents of the A-REGISTER. The operation specified by the ALU OPERATION is executed. Finally, then during GATE-R-TIME gate the result is gated to the condition code logic and DPOUT. The result is not latc...