Browse Prior Art Database

Keyboard Encoder

IP.com Disclosure Number: IPCOM000077645D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Donze, RL: AUTHOR [+3]

Abstract

The keyboard is made up of two sets of key positions. Key 1 is in one set and key 2 is in another set. When key 1 is depressed, capacitor plate 3 moves closer to plates 4 and 5 to increase the coupling between drive line 6 for the A set of key positions and the base of transistor 7. The increased capacitance between plates 4 and 5 allows the Gate Drive A signal to be coupled to the base of transistor 7, causing transistor 7 to conduct and charge capacitor 9.

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Keyboard Encoder

The keyboard is made up of two sets of key positions. Key 1 is in one set and key 2 is in another set. When key 1 is depressed, capacitor plate 3 moves closer to plates 4 and 5 to increase the coupling between drive line 6 for the A set of key positions and the base of transistor 7. The increased capacitance between plates 4 and 5 allows the Gate Drive A signal to be coupled to the base of transistor 7, causing transistor 7 to conduct and charge capacitor 9.

The Gate Drive A signal allows the scan signal to be applied to capacitor plate 4 through AND gate 8. If a key corresponding to the scan signal 1 and Gate Drive A is depressed, the integrator capacitor 9 becomes charged during Gate Drive A time. When the signal on capacitor 9 rises to a predetermined level, the gated Schmitt trigger 10 fires, causing the output signal on line 15 to drop to low-output value.

The detailed circuit diagram of the Schmitt trigger 10 is shown in Fig. 2. In the absence of the -Gate signal, the trigger will fire at a relatively lower level of positive voltage at input terminal 12.

The trigger will not restore to the low-output condition until the input signal at terminal 11 drops to a lower threshold level than would be the case when the -Gate signal is not present.

The output signal on line 15 is interrogated at the end of the Gate Drive A pulse by the AND gate 16, which is conditioned by a -Sample A signal to set latch 17 and provide a low-output signal on line 18. The latch 19 was set before latch 17 became set. Thus, when line 18 provides a low-output signal, it has no effect on latch 19. The output signal on line 20 provides a low output, thus conditioning this leg of the AND gate 21. The combination of low signals on lines 18 and 20 causes a high signal to appear at the output of...