Browse Prior Art Database

Indirect Address Controller

IP.com Disclosure Number: IPCOM000077646D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 48K

Publishing Venue

IBM

Related People

Reed, JW: AUTHOR

Abstract

This controller utilizes the characteristics of semiconductor storage arrays in conjunction with indirect addressing and instruction phase control, to provide a microprogrammed controller.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 4

Indirect Address Controller

This controller utilizes the characteristics of semiconductor storage arrays in conjunction with indirect addressing and instruction phase control, to provide a microprogrammed controller.

A generalized diagram of a static, semiconductor storage array is shown in Fig. 1. The random-access memory is typically organized in an orthogonal matrix with a bistable storage element at each matrix intersection. Address lines are supplied to the matrix to select a particular bistable via the address decode logic. Other array I/O lines are: input data, output data, and write control. An array select line can be used in larger memories.

A read operation is performed by applying an address to the array, waiting until a specified access time has elapsed, and sampling the output data line, as shown in Fig. 2. The read operation is nondestructive and the output data line remains valid until the address lines are changed.

A write operation is performed in a similar manner, except the write control line is raised after the access time has elapsed. The write pulse typically has a minimum width specification (tw). The input data line must be valid before the rise of the write control line, as shown in Fig. 3. The addressed cell data remains valid on the output data line after the access delay, until the write control line is again raised.

The static semiconductor array must provide for a read operation which is nondestructive. In addition, the data output from the array must remain static until the address lines are changed.

A write operation is performed by raising the write control line after the read- access delay has elapsed. The input data line must be valid before the write pulse. The state of the addressed cell appears on the output line during the interval between the end of the read-access delay and the rise of the write pulse.

An indirect addressing scheme utilizing static, random-access storage arrays is shown in Fig. 4. The components are: a local store address register array (LSAR) that contains the address pointers, a data-store buffer, and the portion of the instruction register (ADR) that selects one of the addresses in LSAR. The output of the ADR register is connected directly to the LSAR address inputs, and the output of the LSAR array is connected directly to the data-storage address inputs.

A data-store location is selected according to the following sequence of operations:

1) The ADR portion of the instruction address register is loaded with the address of the LSAR location that contains the data-store address

2) After the LSAR array access time has elapsed, the data-store address is valid on the output of LSAR.

1

Page 2 of 4

3) The contents of the selected data-store location is valid on the data-store output after the access delay.

After the data store has been accessed, the output of the storage array will remain valid until the ADR register is changed.

The same addressing sequence is also performed...