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Fixture for Obtaining Planar Error Correction Pads

IP.com Disclosure Number: IPCOM000077655D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Geldermans, P: AUTHOR

Abstract

It is necessary to provide error-correction pads (EC) for multichip integrated circuit modules. Further, the EC pads must possess a high degree of planarity if suitable wire bonds are to be accomplished on an automatic assembly machine.

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Fixture for Obtaining Planar Error Correction Pads

It is necessary to provide error-correction pads (EC) for multichip integrated circuit modules. Further, the EC pads must possess a high degree of planarity if suitable wire bonds are to be accomplished on an automatic assembly machine.

To insure that the chip carriers all reside in a single plane, the module assembly comprising a substrate 10, solder type interconnection means 12, chip carriers 14, and associated integrated circuit chips 15 are placed in a fixture 18. The fixture 18 includes a plurality of suitable cavities 20 to accommodate the integrated circuit chips 16. Prior to placement in the fixture 18, the integrated circuit chips 16 are bonded to the carrier 14 by an interconnection bond, schematically illustrated at 22.

The entire assembly is then subjected to a joining operation. For example, the assembly can be passed through a solder reflow furnace, so as to integrally bond the chip carriers 14 to the substrate 10 by the plurality of solder reflow interconnections shown at 12. In this manner, all of the chip carriers 14 are assured of being located in a single plane, and thus EC changes can be performed by automatic wire bonding apparatus.

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