Browse Prior Art Database

Digital Sampled Oscillator

IP.com Disclosure Number: IPCOM000077680D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 20K

Publishing Venue

IBM

Related People

McAuliffe, GK: AUTHOR

Abstract

This is a process for generating successive sampled values of a sinewave, which values may be used in digital communication devices.

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Digital Sampled Oscillator

This is a process for generating successive sampled values of a sinewave, which values may be used in digital communication devices.

A new sample value of a sinewave is computed by using one multiplication and one subtraction operation from information of the two previous sample values. The first approximation of samples of the sinewave waveform at uniform spacing result in sin (x + h) = (2 cos h) sin x - sin (x - h)

cos (x + h) = (2 cos h) cos x - cos (x - h).

If successive sampled values of the sinewave are denoted by M(i), M(i+1) = K M(i) - M(i-1) (1).

Thus, in a phase-lock loop, where an oscillator signal is denoted by sin (W(o)t + Phi) The expression would be written as sin [w(o)(t+Delta t)+Phi] = [2cos W(o)Delta t] sin (W(o)t+Phi) sin [W(o)(t-Delta t) + Phi]

K = 2 cos W(o)Delta t.

In order to decrease Phi in a phase-lock loop, K can be decreased from its nominal value by small digital decrements, or, Phi may be increased by decreasing K from its nominal value by small digital increments.

The transfer function in the Z plane has two imaginary poles. Thus, there is a possibility that the computed sign value will grow or diminish, therefore, an addition is made to the expression (1) as follows

1) Increment M(i+1) in magnitude, for example, by rounding it up in magnitude. This addition prevents decay.

2) Remit the maximum amplitude by never permitting M(i+1) to exceed 1, i.e., drop any excess. This prevents instability and growth with...