Browse Prior Art Database

Error Correction System for High Data Rate Systems

IP.com Disclosure Number: IPCOM000077681D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR [+2]

Abstract

A high-data rate system, referred to here as a Page Store Memory, is one that, upon being addressed, will give out a page of words with the words coming out serially at a high data rate. Because of the high rate with which the words come out of a page store, conventional error-correction codes are less than completely suitable.

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Error Correction System for High Data Rate Systems

A high-data rate system, referred to here as a Page Store Memory, is one that, upon being addressed, will give out a page of words with the words coming out serially at a high data rate. Because of the high rate with which the words come out of a page store, conventional error-correction codes are less than completely suitable.

The present error-correction code system is particularly advantageous in handling Page Store Memories. In accordance with the present system, the error correction and detection is implemented by a plurality of coded words which are arranged transverse to the data words making up the page; such coded words include bytes from each of the data words on the page, plus bytes from two check words.

The coded words and the error correction and detection systems involving such coded words are preferably of the cyclic type described in U. S. Patent 3,629,824, D. C. Bossen et al., and in IBM Technical Disclosure Bulletin, October 1971, pages 1549-1552.

In Page Store Memory systems, the data is read out as a series of data words within which the bytes making up the word exit the memory in parallel. Because of such a parallel arrangement, the transverse coded words, which are made up of bytes from each of the data words as well as check bytes, may be applied to the error correction and detection shift registers described in the above-mentioned Technical Disclosure Bulletin article in parallel. Thus, by increasing the shift register circuitry described in the article several-fold, so that there is a complete shift register correction and detection unit for each of the coded words, a dynamic shift register error-correction system for page store memory is made more feasible because speed is greatly increased, while the total circuitry is less than that required by any standard error-correction approach, e.g., an exclusive OR correction approach.

In a standard memory system, ECC, Error-Correction Code, bits are assigned on a word basis. In the example of a 64-bit data word, 8 additional bits are usually provided for SEC/DED (See above article). In the present Page Store system, the data bits used for generating the associated check bits are taken partially from the word direction within individual words, and partially from the multiple-word or page direction. Further, since the individual words come into and out of the memory serially, the check bit generation in encoding and the syndrome generation in decoding may be done using the shift register system described above. In particular, by using codes with a regular structure, the amount of circuitry involved in the shift register type of logic is extremely small, and the check bits or syndrome is available for a block (or page) of words immediately after, or one shift after, the last word of the page is read.

Fig. 1 shows the ECC organization that is described above for a page store. The diagram shows a block of words in a...