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Dendritic Growth Detection Circuit

IP.com Disclosure Number: IPCOM000077682D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Pecoraro, RE: AUTHOR [+2]

Abstract

This dendritic growth detection circuit is a high-input impedance dendritic or ionic electron path detector. The circuit preserves metal migration paths, which otherwise would be destroyed by the high-level biasing necessary to accelerate their propagation in experimental analysis. Without the subject circuit, the dendrites would propagate normally until a current path was formed. At this point, the extreme current density resulting from the bias would destroy them. With the circuit, biasing ceases as soon as a current path is completed.

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Dendritic Growth Detection Circuit

This dendritic growth detection circuit is a high-input impedance dendritic or ionic electron path detector. The circuit preserves metal migration paths, which otherwise would be destroyed by the high-level biasing necessary to accelerate their propagation in experimental analysis. Without the subject circuit, the dendrites would propagate normally until a current path was formed. At this point, the extreme current density resulting from the bias would destroy them. With the circuit, biasing ceases as soon as a current path is completed.

The circuit is activated by utilizing an intrinsic integrating network formed by the relay coil and the turn-on response time of power supply P. S. 1 and the field- effect transistor (FET).

Power supply P. S. 1 is turned on first. Power supply P. S. 2 is then turned on. Since there is no current through the relay coil, the indicator lamp lights, and the FET transistor is still out of the circuit. Power supply P. S. 1 is then turned off. This puts the base bias of the NPN transistor T1 at about ground potential. Transistor T1 turns on, driving transistor T2 on. Collector current from transistors T1 and T2 flows through relay coil, energizing it. This closes the FET source contacts (6 & 8), effectively placing the FET transistor in the circuit. When power supply P. S. 1 is turned on, the voltage on the base of transistor T1 begins to go negative. Before it can go negative enough to turn transistors T1 and T2 off, the FET begins to conduct, supplying sufficient base current to maintain the circuit in an activated state with the FET being the sole supplier of base current due to the voltage divider network action. A reduction in FET conduction would leave the base of tr...