Browse Prior Art Database

Functional and Level Fail Detection for Register Array Testing

IP.com Disclosure Number: IPCOM000077685D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Heavey, PP: AUTHOR [+2]

Abstract

The functionality at up-down levels provided from each cell of a register array are checked in this self-programming detector. Screening is performed for both functional and level fails.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 2

Functional and Level Fail Detection for Register Array Testing

The functionality at up-down levels provided from each cell of a register array are checked in this self-programming detector. Screening is performed for both functional and level fails.

A cyclic output train of all ones or zeros is provided at A from the random- access memory under test to a signal divider 1. As shown in the waveform diagram, the waveform at A has one failing bit indicated in dotted form. Signal divider 1 provides the input waveform to two paths including an adjustable delay circuit 2 and a signal inverter 3. The outputs of circuits 2 and 3 are indicated as waveforms B and C, respectively. In the functional screening portion of the test circuit, the B and C signals are combined at signal combiner 4 into waveform D which is provided to AND 5 along with a clock reference. AND 5 acts as an A to D comparator to detect a failure in the train provided at A. When AND 5 provides an output, a failure latch 6 is set providing an indication of a functional fail at 7.

In the level screening portion of the circuit, AND gates 8 and 9 are provided to receive the B and C waveforms, respectively. A DC uplevel reference is provided to AND 8 at 10 and a DC down-level reference is provided to AND 9 at
11. These reference levels are the minimum acceptable levels for the register array under test. By the AND gates 8 and 9, the levels are screened and if the comparison indicates a failure by waveforms B an...