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Test System for Narrowing the Range of Performance Characteristics of Monolithic Integrated Circuits

IP.com Disclosure Number: IPCOM000077688D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

A test scheme is provided for narrowing the range of performance characteristics of monolithic integrated circuits, particularly field-effect transistor (FET) chips, so that a given set of chips mounted on a particular card have performance speeds and power dissipation within a relatively narrow range. The performance ranges of field-effect transistor products at the system level can be narrowed by separating the chips at the chip level into groups having similar characteristics, and then mounting chips of similar characteristic on the same card at the card level.

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Test System for Narrowing the Range of Performance Characteristics of Monolithic Integrated Circuits

A test scheme is provided for narrowing the range of performance characteristics of monolithic integrated circuits, particularly field-effect transistor (FET) chips, so that a given set of chips mounted on a particular card have performance speeds and power dissipation within a relatively narrow range. The performance ranges of field-effect transistor products at the system level can be narrowed by separating the chips at the chip level into groups having similar characteristics, and then mounting chips of similar characteristic on the same card at the card level.

In the MOSFET technology, there is a tendency for a great variation in characteristics of chips produced by identical monolithic fabrication processes. As a result, for some of the circuits presently employed in FET integrated circuits, the performance characteristics can differ by as much as 100% due to tolerances of threshold voltage. Because of these wide differences, there are at one end of the distribution curve chips exhibiting fast response time and high-power dissipation, and at the other end of the distribution curve there are chips having slower circuit response time and lower-power dissipation.

With the present testing method, the FET chips are sorted at the chip level during testing into two categories: those having fast performance time and high- power dissipation and those having slower res...