Browse Prior Art Database

Pulse Generating Circuits

IP.com Disclosure Number: IPCOM000077721D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Barsotti, RH: AUTHOR

Abstract

A single timer times the trailing edges of pulses in a plurality of channels, respectively. The single timer is particularly useful in write-amplitude compensation techniques in multiple track magnetic tape recorders.

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Pulse Generating Circuits

A single timer times the trailing edges of pulses in a plurality of channels, respectively. The single timer is particularly useful in write-amplitude compensation techniques in multiple track magnetic tape recorders.

The write-amplitude compensation shown in the waveform sketch is that taught by Ambrico in U. S. Patent 3,503,059. In that patent, the extra amplitude at the beginning of each data pulse after a long one-half wavelength, compensates for phase shift in magnetic recording systems. The leading edge of each pulse is determined in each of the various track circuits in accordance with present techniques. The single timer simultaneously generates the trailing edge of the higher amplitude portion as at 10, 20, and 30. As will be explained, the duration of the write-amplitude-portion of the data pulse may vary slightly in accordance with electronic skew of the recording system. Phase information at the leading edge of each pulse remains the same, so there is no added phase shift in any track caused by using a single timer.

Each separate channel or track has its own driver or write circuit constructed in accordance with the Ambrico patent or suitable equivalents. Dash boxes 40 contain diagrams illustrating circuitry for each track for effecting single timer control. Each circuit 40 receives its channel input data signals in true (+) and complement (-) form. AND's A1 and A2, respectively, pass a change in phase over lines 01 and 02 for positive and negative compensation to the respective channel-driver circuits. The illustrated phase holds memorize polarity of the signal on the write bus, in the channel driver circuit, etc. The leading input data signal controls the timer for truncating write compensation time as follows. Initially, the timer enables the phase holds to capture the polarity of the signals on the + lines. Upon the first change in any of the channels, either A1 or A2 supplies a control signal over cable 50 through OR to initiate the timer. Then all AND's A1 and A2, re...