Browse Prior Art Database

Small Area Stored Charge Memory Cells

IP.com Disclosure Number: IPCOM000077732D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

Figs. 1 and 2 show a plan and side view, respectively, of a charge-coupled device memory cell of small area having minimum word pitch. Fig. 2 shows a cross-sectional view of the layout of the charge-coupled device cell of Fig. 1. In Fig. 2, a semiconductor wafer 1 contains bit line diffusions 2 which are covered by regions of thick silicon dioxide 3. A polysilicon gate 4 is spaced from the surface of wafer 1 by a thin layer of silicon dioxide 5 and a layer of silicon nitride 6. By applying an appropriate potential to polycrystalline silicon gate 4, a storage region, or well, is produced in silicon wafer 1.

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Small Area Stored Charge Memory Cells

Figs. 1 and 2 show a plan and side view, respectively, of a charge-coupled device memory cell of small area having minimum word pitch. Fig. 2 shows a cross-sectional view of the layout of the charge-coupled device cell of Fig. 1. In Fig. 2, a semiconductor wafer 1 contains bit line diffusions 2 which are covered by regions of thick silicon dioxide 3. A polysilicon gate 4 is spaced from the surface of wafer 1 by a thin layer of silicon dioxide 5 and a layer of silicon nitride
6. By applying an appropriate potential to polycrystalline silicon gate 4, a storage region, or well, is produced in silicon wafer 1. A layer of thermally grown silicon dioxide 7 covers the surface of polycrystalline silicon gate 4 and, in conjunction with a portion of silicon nitride layer 6 and thick oxide layer 3, permits a metal line 8 to extend in insulated spaced relationship over semiconductor wafer 1 and polycrystalline silicon gate 4.

A portion 9 of metal line 8, which is contiguous with a portion of silicon nitride layer 6, acts as a transfer gate for transferring charge from bit line diffusion 2 to the storage region, or well, formed in wafer 1 by the application of an appropriate voltage on polysilicon gate 4. From this, it may be seen that metal line 8 acts as a word line which, when energized with an appropriate potential, provides transfer gates 9 which are simultaneously energized for a plurality of charge-coupled devices similar to that just described.

The fabrication process for the charge-coupled device of Figs. 1 and 2 is as follows:
1) Grow thin oxide over wafer 1 (for example, 300 Angstroms).
2) Deposit thin nitride layer over the oxide (for example,

300 Angstroms).
3) Delineate oxide/nitride layers for diffusion of bit lines

2 (mask #1).
4) Diffuse dopant into semiconductor wafer.
5) Remove nitride selectively (mask #2).
6) Regrow thick oxide.
7) Deposit polycrystalline silicon.
8) Delineate and oxidize polysilicon (mask #3).
9) Deposit a layer of refractory metal.
10) Delineate refractory metal into word lines (mask #4).
11) Protect a strip of polycrystalline silicon (mask #5).
12) Etch polycrystalline silicon, using mask #5 and refractory

metal as etch resists to define polycrystalline pattern.
13) Regrow thick oxide.

Fig. 3 and 4 show a single device field-effect transistor memory device of the type shown in U.S. Patent 3,387,286 issued June 4, 1968 and assigned to IBM. In Fig. 3 which shows the layout of the memory cell and Fig. 4 which is a cross- sectional view taken along lines 4-4 of Fig. 3, silicon wafer 11 contains diffusions 1% of opposite conductivity type to that of wafer 11, which act as sources and drains of one-device memory cells. Wafer 11 also contain...