Browse Prior Art Database

Synchronous Sequential I/O Control Unit

IP.com Disclosure Number: IPCOM000077765D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

Ballou, DC: AUTHOR

Abstract

Fig. 1 is a simplified block diagram of a typical computer system. Communication between the CPU 10 and the I/O devices 30 is accomplished via interlocking signal sequences between channel 15 and I/O control units 20. The signal sequences on the I/O interface are standard and are monitored by the I/O control units simultaneously. The interface between the I/O control units 20 and the I/O devices 30 is unique, depending only on the particular I/0 control unit and device involved.

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Synchronous Sequential I/O Control Unit

Fig. 1 is a simplified block diagram of a typical computer system. Communication between the CPU 10 and the I/O devices 30 is accomplished via interlocking signal sequences between channel 15 and I/O control units 20. The signal sequences on the I/O interface are standard and are monitored by the I/O control units simultaneously. The interface between the I/O control units 20 and the I/O devices 30 is unique, depending only on the particular I/0 control unit and device involved.

Fig. 2 is a block diagram of a synchronous I/O control unit. This type of control unit can be used to attach any device to various models of IBM S/360 or S/370 computer systems. All I/O control units 20 have receivers 21; drivers 22; on/off line control 23; select-out bypass relays 24; address decode 25; command, sense and status registers 26; clock 27; control circuit 28; and regulation circuit
29. In this instance, the I/O regulator 29 is a synchronous sequential circuit, rather than combinational logic with single-shots or an unclocked sequential circuit. I/O regulator 29 performs all the signal interlocking sequences with channel 15, gates commands, status, sense and data to and from associated devices 30 and controls all functions of I/O control unit 20.

Fig. 3 is a state diagram for I/O regulator 29. Each state is a memory element which remembers the previous operation and is a step in a sequence. Each state performs an operation such as raising a signal response to the channel or gating data, status, sense or commands. I/O regulator 29 is essentially in one state at a time. When shifting to a new state, the previous state is reset. The decision to shift to a new state is determined by the following conditions: (1) the present state, (2) the inputs from channel 15, (3) the inputs from associated device 30, and (4) the clock time from 27. If the conditions required to cause shifting to the next state are not met, I/O regulator 29 remains in its present state until the conditions are met. In some states, the next state is predetermined and the four conditions mentioned will decide when to shift. In other instances, there may be more than one poss...