Browse Prior Art Database

High Density and Speed Performance Chip Joining Procedure and Package

IP.com Disclosure Number: IPCOM000077768D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Iafrate, PF: AUTHOR

Abstract

The use of mirror-image integrated circuit chips 10 and 12 allows contact terminals 14 on each chip that may be common, to be connected by metal conducting lines 16, deposited in ceramic substrate 18. Use of such back-to-back chips 10 and 12 enables elimination of separate conducting lines for terminals 14 that may be common, such as power terminals. This reduces both the number and length of required conducting lines on substrate 18. Contact pins 20 are provided in a conventional manner for the package.

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High Density and Speed Performance Chip Joining Procedure and Package

The use of mirror-image integrated circuit chips 10 and 12 allows contact terminals 14 on each chip that may be common, to be connected by metal conducting lines 16, deposited in ceramic substrate 18. Use of such back-to- back chips 10 and 12 enables elimination of separate conducting lines for terminals 14 that may be common, such as power terminals. This reduces both the number and length of required conducting lines on substrate 18. Contact pins 20 are provided in a conventional manner for the package.

If desired, separate substrate members may be used for mounting of the chips, rather than a single substrate 18. The two substrates are then bonded back-to-back to produce a structure similar to that shown.

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