Browse Prior Art Database

Field Effect Transistor Memory Circuit

IP.com Disclosure Number: IPCOM000077778D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

LeBlanc, AR: AUTHOR

Abstract

The random-access memory circuit uses a layer 10 of high-dielectric material, such as silicon nitride, Si(3) N(4), in the storage capacitor 12 to reduce the size of each memory cell area.

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Field Effect Transistor Memory Circuit

The random-access memory circuit uses a layer 10 of high-dielectric material, such as silicon nitride, Si(3) N(4), in the storage capacitor 12 to reduce the size of each memory cell area.

The circuit includes a field-effect transistor 14 formed in, for example, a P- type silicon wafer 16 with suitable spaced apart N-type regions 18 and 20 and a gate electrode 22 disposed between the regions 18 and 20 on a layer of silicon dioxide 24. Metallic electrode 26, which may be made of aluminum, contacts one surface of the Si(3)N(4) layer, while the other surface of this layer is in contact with N-type region 20. N-type region 18 is contacted by metallic electrode 28 which may also be made of aluminum. A word line driver 30 connected to gated electrode 22 applies control pulses to field-effect transistor 14, and bit line driver and sense amplifier 32 is used to write binary information into and read information out of storage capacitor 12.

The processing steps for this circuit are as follows:
1) After heavily diffusing suitable H-type impurities into

regions 18 and 20, a layer of SiO(2) is formed on silicon

wafer 16.
2) The SiO(2) layer between N-type regions 18 and 20 and over

N-type region 20 is etched.
3) A thin SiO(2) layer is grown in the opening formed by step 2.
4) The thin SiO(2) layer formed over N-type region 20 is etched.
5) The Si(3)N(4) layer 10 is disposed over N-type region 20.
6) An opening is provided over the N-type...