Browse Prior Art Database

Multiplexing Parallel Scrambler Descrambler

IP.com Disclosure Number: IPCOM000077789D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

Described is a scrambler-descrambler unit, which is capable of providing a scrambled coding for data characters to be transmitted and for unscrambling code received from a distant terminal. The unit processes a full character of data in one processor cycle, and one unit can be utilized in a multiplexed manner to scramble and unscramble the data to and from a plurality of transmission lines.

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Multiplexing Parallel Scrambler Descrambler

Described is a scrambler-descrambler unit, which is capable of providing a scrambled coding for data characters to be transmitted and for unscrambling code received from a distant terminal. The unit processes a full character of data in one processor cycle, and one unit can be utilized in a multiplexed manner to scramble and unscramble the data to and from a plurality of transmission lines.

As shown in Fig. 1, a main storage unit 1 contains a storage area for each transmission line whose data is to be processed. The storage area will be selected by the address of the corresponding line sent in on line address bus 2 and will provide storage for at least a seven-bit scrambler residue, seven-bit character data, and a transmit-receive indicator along, with any other line related data to be stored. When an unprocessed character has been stored in a lines area of storage 1 and the line address bus 2 addresses the line, the residue is read out to current residue (CR) register 3, the input data is placed in the input data (ID) register 4, and the transmit-receive bit is sent to a control 6 to set it for the proper type of operation. The data in registers 3 and 4 are combined in a seven-part combinational logic 7 which produces both an updated residue in buffer 8 and a scrambled or descrambled character in buffer 9, depending on the setting of control 6. The updated residue of buffer 8 is returned over bus 10 to the main storage 1 for storage in the residue part of the lines storage, and the contents of buffer 9 are available on bus 11 for continued processing.

Each part of the combinational logic 7 is as shown in Fig. 2, which shows the leftmost part of the logic where and "X" AND circuit 12 receives seven signal inputs and a "W" AND circuit 13 receives the same seven input in a complemental phase. The output of AND 12 is inverted in inverter 14 whose output is suppl...