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Parallel CRC Generation for Multilength Characters

IP.com Disclosure Number: IPCOM000077790D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Boudreau, PE: AUTHOR [+4]

Abstract

The drawing is a schematic diagram of a Cyclic Redundancy Check (CPC) generator for parallel generation of the CRC polynomial, for characters of variable length. In the drawing, an Old CRC register 1 has a storage length equal to the number of bits in the CRC polynomial being generated, here shown as 16 bits, and a character register 2 has a length sufficient to store the maximum bit length of a character to be processed. When a new CRC sum is to be generated, the bits stored in the character register 2 are exclusive Ored in unit 3 individually with the low-order bits of the Old CRC register 1 to provide an eight-bit output on cable 4. If the character being entered has less than the full eight-bit capacity, the higher order positions, i.e.

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Parallel CRC Generation for Multilength Characters

The drawing is a schematic diagram of a Cyclic Redundancy Check (CPC) generator for parallel generation of the CRC polynomial, for characters of variable length. In the drawing, an Old CRC register 1 has a storage length equal to the number of bits in the CRC polynomial being generated, here shown as 16 bits, and a character register 2 has a length sufficient to store the maximum bit length of a character to be processed. When a new CRC sum is to be generated, the bits stored in the character register 2 are exclusive Ored in unit 3 individually with the low-order bits of the Old CRC register 1 to provide an eight-bit output on cable 4. If the character being entered has less than the full eight-bit capacity, the higher order positions, i.e., 0, 1, and 2, which are not utilized by the character must be filled with logical zeros.

The output of exclusive OR unit 3, together with the remaining eight bits from Old CRC register 1 on a bus 5, form the 16 inputs of a shifter 6 which is capable of shifting the input data from busses 4 and 5 either zero, one, two or three positions to the left. A set of control lines 7 are energized according to the length of character being entered to shift the input signals. The shift is from zero for an eight-bit character to three for the five-bit characters. The 19 outputs of shifter 6 are gated into an P register 8 for temporary retention. From R register 8, the outputs, representing an intermediate CRC sum, pass through an exclusive Or network 9 to generate the final CRC sum of 16 bits, which is returned over bus 10 and gated into the Old CRC register 1 for combining with the next new character to be entered in character register 2.

The exclusive Or network 9 will be connected in di...