Browse Prior Art Database

Address Generator

IP.com Disclosure Number: IPCOM000077803D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Honkala, JE: AUTHOR [+2]

Abstract

The minimum addressing sequence required for AC testing all possible to/from input combinations of a multiple input read-only memory or similar logic device, is provided by this address generator. All redundancy in the addressing sequence is eliminated reducing the time required for testing.

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Address Generator

The minimum addressing sequence required for AC testing all possible to/from input combinations of a multiple input read-only memory or similar logic device, is provided by this address generator. All redundancy in the addressing sequence is eliminated reducing the time required for testing.

The generator includes "TO" register 1, "FROM" register 2 and precondition register 3. Registers 1-3 are synchronous, up-down counters with load capability. Gate circuits 4, 5 are provided for coupling to registers 1, 2, respectively, and loading control circuits 6, 7 operate with respect to registers 1 and 3, respectively. Loading control circuit 7 is also coupled to set-reset flip-flop which is operable under the control of a master clock.

In operation, when register 2 is at zero count, register 3 at a one count and load lines 10, 12 to registers 3 and 1, respectively, are active, register 1 contains a one count. Line 13 to register 2, line 9 to register 3 and line 11 to register 1 are inactive as is clear line 14 to register 2. At the initial time, the contents of register 2 are gated to register 15 and from this register to device under test 16. On the first clock pulse to flip-flop 8, the contents of register 1 are gated out. At this time, line 12 to register 1 and line 10 to register 3 are active.

The next clock pulse gates out the contents of register 2. Lines 10 and 12 go to an inactive status and line 11 becomes active advancing register 1 to a count of two. Switching occurs back and forth between registers 1 and 2. Each time register 2 is gated out, the contents of register 1 is advanced by a count of one. This process continues until register 1 becomes full, that i...