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Forming Patterns on The Back of Wafers in Proper Alignment to the Patterns on The Front of Wafers

IP.com Disclosure Number: IPCOM000077805D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Chiu, TL: AUTHOR [+2]

Abstract

In this method a layer of oxide or insulator 10 is grown or deposited on semiconductor substrate 11, as shown in the figure. Using photolithographic and etching techniques, part of oxide layer 10 is removed from windows 12. Then preferential silicon etch, such as a mixture of 40 mol% H(2)O,5 ethylenediamine, and 2 mol% pyrocatechol is used to etch windows 13 through substrate 11. The oxide layer 10 is then removed. All the patterns to be formed on the front and the back of wafers are aligned to the front side and the back side of windows 13, respectively. Thus, the patterns on the back of wafers can be aligned properly to the patterns on the front of wafers - the windows serving as reference marks.

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Forming Patterns on The Back of Wafers in Proper Alignment to the Patterns on The Front of Wafers

In this method a layer of oxide or insulator 10 is grown or deposited on semiconductor substrate 11, as shown in the figure. Using photolithographic and etching techniques, part of oxide layer 10 is removed from windows 12. Then preferential silicon etch, such as a mixture of 40 mol% H(2)O,5 ethylenediamine, and 2 mol% pyrocatechol is used to etch windows 13 through substrate 11. The oxide layer 10 is then removed. All the patterns to be formed on the front and the back of wafers are aligned to the front side and the back side of windows 13, respectively. Thus, the patterns on the back of wafers can be aligned properly to the patterns on the front of wafers - the windows serving as reference marks.

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