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High Performance FET Device Structure and Method

IP.com Disclosure Number: IPCOM000077807D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Gaind, AK: AUTHOR

Abstract

This device has a very short channel length beneath the gate electrode which increases its speed.

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High Performance FET Device Structure and Method

This device has a very short channel length beneath the gate electrode which increases its speed.

The speed of a field-effect transistor (FET) is inversely proportional to the square of the channel length. The minimum channel length in an FET device is limited, in general, to 100 microinches by photolithographic limitations. The channel length can be reduced further by making source and drain diffusions by the self-aligned gate technique, where the diffusions extend under the gate. Thus, the channel length is significantly less than the gate width. However, the gate overlap increases the input Miller capacitance which delays the circuit. The disadvantage is that the gain in speed is less than expected by the inverse- square rule.

In this device, the channel length 10 beneath gate electrode 12 is reduced by diffusing only the source 14 beneath the electrode 12. The drain region 16 extends only slightly beneath electrode 12. The gate overlap of the drain region is not as pronounced as the gate overlap of the source region. Consequently, a device fabricated as shown, will be significantly faster than a device having equal overlap of the gate in source and drain regions.

The structure can be fabricated by defining the gate 12, preferably with a SiO(2), and Si(3),N(4) layer, reoxidizing the surface of the wafer, opening the diffusion window for the source region 14 utilizing the edge of the gate as one edge of the openi...