Browse Prior Art Database

Improving the Performance of an Existing Processor

IP.com Disclosure Number: IPCOM000077818D
Original Publication Date: 1972-Sep-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Alvarez, JA: AUTHOR [+6]

Abstract

Fig. 1 shows a pipelined two instruction stream processing unit, intended as a high-performance attachment to an existing processor via a field effect (FET) memory bus. The high-performance attachment controls the system and executes the high incident fixed-point instruction subset of the system, and utilizes the existing processor as an unoverlapped execution unit for instructions outside this high-incident instruction subset

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Improving the Performance of an Existing Processor

Fig. 1 shows a pipelined two instruction stream processing unit, intended as a high-performance attachment to an existing processor via a field effect (FET) memory bus. The high-performance attachment controls the system and executes the high incident fixed-point instruction subset of the system, and utilizes the existing processor as an unoverlapped execution unit for instructions outside this high-incident instruction subset

This system provides the capability to execute frequently encountered instructions at a high rate from the two I streams and to issue all other instructions to the existing processing unit. The existing processing unit operates essentially unoverlapped for the low-usage instructions. The instructions executed in the high-performance attachment are basic all the fixed-point arithmetic logical instructions and branch instructions. The instructions executed in the existing processor consists of the floating point, VFL, and decimal instructions.

HIGH-PERFORMANCE ATTACHMENT:

The high-performance attachment is pipelined, i.e., an instruction is passed through several registers during execution. Each register controls an instruction during a certain stage of its execution (e.g., operand address generation). The high-performance attachment is also overlapped so that its several instructions can be at various stages at the same time. I-UNIT EXECUTION FACILITY:

The I-Unit execution facilities consist of an adder and a shifter. The adder is used for address calculation and fixed-point execution (including the logical operations). A zero to three bit shifter is provided to execute SLL, SRL, SLA and SRA instructions. AL1 of the shift instructions or those shift instructions whose length exceeds three are sent to the existing processor for execution. CACHE FACILITY:

The cache facility is a high-speed local buffer, which supplies data instructions to the two I Streams in the high-performance attachment. A word may be requested from the cache facility by presenting to it a real or logical address along with its I-Stream tag. In addition to buffering data fetched from main storage, the cache facility is responsible for translating the logical address of the request word, checking a directory table to insure that the requested word is cache resident, and providing the associated storage protect key of the requested word. If no ex...