Browse Prior Art Database

Buffering for High Speed Data Transfer

IP.com Disclosure Number: IPCOM000077858D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Related People

Wade, FL: AUTHOR

Abstract

Described is a method of buffering data in a control unit connected to a channel, which operates in an interlock manner with two tags designated Service Out, Data Out from the channel to the control unit and two tags designated Service In, Data In from the control unit to the channel. The operation of the tag lines themselves is described in U. S. 3,582,906.

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Buffering for High Speed Data Transfer

Described is a method of buffering data in a control unit connected to a channel, which operates in an interlock manner with two tags designated Service Out, Data Out from the channel to the control unit and two tags designated Service In, Data In from the control unit to the channel. The operation of the tag lines themselves is described in U. S. 3,582,906.

Fig. 1 shows a block diagram of data transfer hardware for write mode. Two data buffers, Buffer A and Buffer B, transfer data in either direction between a storage control unit and a channel. The loading is controlled by the state of four latches: Transfer A latch, Transfer B Latch, Control Response Flip-Flop, and Channel Response Flip-Flop, as well as by control signals from the storage control unit.

During a write operation where data is transferred from the channel to the control unit, data transfer proceeds as follows. Initially, the Channel Response latch 1 is reset which enables the Data In line 5 via AND gate 3, and disables the Service In line 9 via AND gate 7. The Control Response Flip-Flop is reset steering the contents of Buffer A to the input register via buses 11, gate 13 and bus 15. The control unit sets the hardware to write mode, internal to the control unit. Since Transfer A Latch 17 is initially reset, Data In conditions AND 3 inasmuch as it assumed that Data Out is down at this time. Therefore, Data In rises to request the first byte from the channel. When the first byte is available on the Channel Bus 21, the channel responds by raising Data Out line 23. This line sets the Channel Response latch 1 overline 2321 sets Buffer A 25 with the data from the channel bus and sets Transfer A Latch 17. The state of Control Response Flip-Flop 27 (reset) and Channel Response Flip-Flop 1 (set) are compared at 28, and if they are the indicated states (miscompare), then Buffer A is gated to the input register which is synchronized to be set at the appropriate time. The comparison ensures that the sequential data transfer mechanism is in step and protects data integrity. Also, Transfer A Latch activates Transfer Branch line 29 via OR 31, indicating to the control mechanism of the storage control unit that a byte is available in the input register.

The setting of Channel Response latch 1 deactivates Data In by inhibiting AND gate 3. Since Buffer B is available inasmuch as Transfer B Latch is not yet set, Service In is raised by line 33 activating AND gate 7, so as to request the second byte from the channel. Since Data In has dropped, the channel drops Data Out. When the second byte is available on the channel bus, the channel responds with Service Out on line 35. Service Out resets the Channel Response latch 1, sets Buffer B with the data from the channel bus and sets Transfer B latch which sets or maintains Transfer Branch line 29.

If the Control Response Flip-Flop 27 is off, the preceding byte is still in the input register. Buffer B...