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Zero Crossing Detector

IP.com Disclosure Number: IPCOM000077860D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Liu, CC: AUTHOR [+3]

Abstract

This detector relates generally to a signal amplifying, limiting and pulse forming circuitry. and more particularly to an improved data transition detection circuit. In frequency modulation read channels, the readback head signal is generally applied to a preamplifier, a differentiator, and a limiter. The amplitude limited signal is then applied to a transition detection circuit. The leading edge of the detected pulse output coincides with the zero crossing of the incoming signal.

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Zero Crossing Detector

This detector relates generally to a signal amplifying, limiting and pulse forming circuitry. and more particularly to an improved data transition detection circuit. In frequency modulation read channels, the readback head signal is generally applied to a preamplifier, a differentiator, and a limiter. The amplitude limited signal is then applied to a transition detection circuit. The leading edge of the detected pulse output coincides with the zero crossing of the incoming signal.

Fig. 1 shows the diagram for the limiting amplifier stages and for the transistor detection circuit. Limiting Amplifier Stages.

T1 and T2 form a differential transistor pair with the transistor clamp loads R1, R2 and T3; R3, R4 and T4. The input base bias voltage and resistor values of R1 through R5 are chosen to provide a linear gain in the transition region of the input signal. T5, T6, R6 and R7 are emitter-follower circuits for impedance isolation between stages.

A feature of this circuit is the provision of a DC coupled limiting amplifier stage, which can be used repetitively in a given construction and provide both the overall circuit gain and clamping level. This feature eliminates the need of using a level-shifting circuit or PNP transistor stage in most conventional designs. Transition Detection Circuit.

The basic transition detection circuit is an emitter-coupled transistor pair T7, T8, with two identical current sources I1, I2, as shown. timing capacitor Cx is connected between the two emitters. T9, T10, together with R8, R9. R10 and R11 are transistor clamp circuits and serve as collector loads to T7 and T8, respectively. The collector loads are OR'd together through T11 and T12. R12 and R13 are line terminating resistors at the output. The output follows the more positive base potential of T11 and T12.

The signal at the in...