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FET Hysteresis Circuit

IP.com Disclosure Number: IPCOM000077885D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Christopherson, WA: AUTHOR

Abstract

An input circuit for field-effect transistor (FET) logic chip converts a noisy external input into a relatively noise-free logic-level, while minimizing power dissipation.

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FET Hysteresis Circuit

An input circuit for field-effect transistor (FET) logic chip converts a noisy external input into a relatively noise-free logic-level, while minimizing power dissipation.

At the input section of the circuit, FET devices T1, T2 and T3 are arranged to form a voltage dividing network for the input voltage Vin. T1 is designed to conduct a low current compared to T2. since it is not needed for turn on action of T4. The output of the voltage dividing network is designed to provide a latching effect (i.e. snap action) for T4, by a feedback connection between T4 and T3 of the input section. T5 is any FET load device, such as a resistor. T5 is usually another FET device connected in such a manner that it is always in a conducting (on) state. Its function is to furnish current to pull up the output node when T4 is off.

If it is assumed that Vin is at 0 volt and T4 is off, then the gate of T3 is up and T3 is on. With T3 on, the voltage V(g4) at the gate of T4 is minimized. However, as Vin rises, V(g4) eventually rises sufficiently past the threshold so that T4 conducts.

Then T3 is turned off by the feedback connection from T4, and the full input voltage is applied to the gate of T4 via T2 and T1.

The snap (regenerative) action of this T4 turnon is accompanied by a large decrease in the Vin "on" threshold (of the order of from 2.5:1, to 5:1 over the worst case range of process-parameter variations and dimensional tolerances). Thus, once T4 is on, a la...