Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Queue System for a Two Program Pipelined Instruction Unit

IP.com Disclosure Number: IPCOM000077916D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Fennell, JW: AUTHOR

Abstract

Fig. 1 shows an I-unit pipeline for use in a two-program, pipelined processor. The queue system accepts instructions after completion of an address calculation cycle. An instruction leaves the queue when it is ready for execution. Other characteristics of the pipeline are: 1) Two independent instruction streams are present in the pipeline. 2) The address calculation stage services only one instruction per cycle. It is shared by both programs. 3) The execution stage can service only one instruction per cycle. It is also shared by both programs. 4) A General Purpose Register (GPR) read system is shared by the address calculation stage and the execution stage. Only one stage can do a CPR read per cycle. The queue system: 1) Accepts instructions from the address calculation stage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Queue System for a Two Program Pipelined Instruction Unit

Fig. 1 shows an I-unit pipeline for use in a two-program, pipelined processor. The queue system accepts instructions after completion of an address calculation cycle. An instruction leaves the queue when it is ready for execution. Other characteristics of the pipeline are:
1) Two independent instruction streams are present in the

pipeline.
2) The address calculation stage services only one instruction

per cycle. It is shared by both programs.
3) The execution stage can service only one instruction per

cycle.

It is also shared by both programs.
4) A General Purpose Register (GPR) read system is shared by the

address calculation stage and the execution stage. Only one

stage can do a CPR read per cycle.

The queue system:
1) Accepts instructions from the address calculation stage.
2) Keeps instructions from a given program in order.
3) Allows instructions from one program to pass instructions from

the other, while maintaining instructions from a given

program in order.
4) Selects an instruction from the queues for execution.
5) Controls CPR read priority, giving the execution stage

priority over the address calculation stage.
6) Shares hardware.

Fig. 2 shows the queue system. Queues 0 and 1 can be used by both programs. Queue A can be used only by program A and is also a checking station for program A. Queue B performs the same function for program B.

Checking stations A and B perform identical functions; they check to see if an instruction is qualified to go to the execution stage. For example, if an instruction has made a memory access in the address calculation stage, a check is performed to assure the operand will be available at execution time. If the instruction reads or modifies a GPR in execution, a check is done to insure the GPR is valid for that operation. Checks in QA and QB are done simultaneously. One machine cycle i...