Browse Prior Art Database

Josephson Device Equality Comparator

IP.com Disclosure Number: IPCOM000077919D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Landman, BS: AUTHOR

Abstract

Operation of the device is based upon a linear Josephson junction gate device having symmetrical characteristics. That is, if the magnitude of the input current to a Josephson gate is standardized, then a total control current flowing in either direction will switch the gate from V = 0 to V = 2 delta, and a cancellation of the input currents provides a net control current insufficient to switch the gate from the V = 0 state.

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Josephson Device Equality Comparator

Operation of the device is based upon a linear Josephson junction gate device having symmetrical characteristics. That is, if the magnitude of the input current to a Josephson gate is standardized, then a total control current flowing in either direction will switch the gate from V = 0 to V = 2 delta, and a cancellation of the input currents provides a net control current insufficient to switch the gate from the V = 0 state.

The device illustrated provides a bit-by-bit comparison of digital words A = (An-1,.., A1, A0) and B = (Bn-1,.., B1, B0). A logical output of "0" is provided if all bits are equal and an output of "1" if any bit is unequal. Josephson gates Go through Gn-1 are provided, each coupled by a bit line A0 through An-1 and B0 through Bn-1, wherein each of the lines A and B are oppositely coupled. The gates G have outputs connected in series to a bias source I(1), and an input to an output gate through transmission lines Zo and terminating impedance 2Zo. The direction of currents provided by inputs A and B to gate G are indicated by the direction of the arrows. It can be seen that any inequality of bit input will switch a particular gate G and hence the output gate, while only total equality of inputs will provide no output.

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